A variety of sensing techniques have been employed for retrieving data from non-volatile memory arrays. Generally, these consist of a means of connecting a plurality of memory cells to a data input of a sense amplifier or comparator circuit and a reference quantity (either a reference potential or a reference current) to a reference input of the same comparator circuit. This comparator determines the binary state of the connected memory cell.
A benchmark of the state of the art in this field is defined by the quality of the reference quantity provided to the comparator circuit. A differential memory cell which consists of two single non-volatile memory cells programmed to opposite binary states would be ideal in that the reference and data quantities both would be provided by the memory cell. Well understood differential sensing techniques could be applied readily to such a differential memory cell. However, this arrangement requires two memory devices to store one bit of data.
In practice, a single ended memory cell is used in favor of the differential cell. A plurality of single ended cells is connected to the data input of a comparator circuit and a single reference quantity is provided as the comparator's reference input. Although less robust than the differential memory cell, the single ended memory cell is approximately half the size of the differential memory cell. Work in this area has focused on generating a suitable reference quantity and appropriate sensing circuitry which can utilize the reference to determine the binary state of the memory cells.
In non-volatile memories, the data storage element is the floating gate of an MOS transistor. The charge on this floating gate is altered by one of three methods: charge can be removed by exposing the data storage elements to ultraviolet light, charge can be added by generating hot electrons in the immediate vicinity of the data storage element, and charge can be either added or removed by tunnelling electrons across a thin oxide. The end result is a shift in the threshold voltage of the MOS transistor and, under proper biasing, a difference in conductivity can be created. In a non-volatile memory application, a high conductivity state and a low conductivity state are created using one of the three methods of altering charge on the floating gate.
In U.S. Pat. No. 4,301,518 a single dummy EPROM cell is connected in series to a resistive load device (an MOS transistor in the specific embodiment). This resistive divider provides a reference voltage to a differential sense amplifier. Data cells are connected in an identical series fashion to a similar load device which has one half of the resistance of the reference load device (mentioned in column 4, line 25 of the text). In effect, the dummy cell current and data cell current flow in two differently valued resistive loads, thus creating a differential voltage which can be sensed. In this invention, the load devices must be carefully crafted to match the characteristics of EPROM cells so as to provide inputs to the sense amplifier which do not exceed the input range of the sense amplifier.
In U.S. Patent No. 4,713,797 a current reference is provided to the reference input of a current comparator. This current is provided by a dummy cell programmed to a high conductivity state. The data input to the current comparator comes from a memory cell connected in the same fashion as the dummy reference cell. However, through current mirroring and MOS device scaling, which are well understood in the art, the data current is doubled. In effect, the reference current is compared to two times the data current. Although functional, this method suffers from the disadvantage that the low conductivity state of a memory cell must provide less than half of the current of a high conductivity cell (the reference) or the circuit will not sense the proper state of the memory. While this condition is virtually certain in a properly designed non-volatile memory, the data retention time of the memory system will be limited by this deficiency.
U.S. Pat. Nos. 4,301,518 and 4,713,797, mentioned above, use a dummy cell whose conductivity is substantially the same as one of the binary states of the data memory cells. Circuit techniques are used in the comparator logic to sense the state of the memory cells. In other patents, a different approach was taken. In one such alternative approach the dummy cell itself is altered to provide a current reference which is between the erased and written values of the programmed data memory cells.
For example, in U.S. Pat. No. 4,434,479 the reference memory cell is substantially identical to the data memory cells. However, the programming logic for the reference cells permits programming them to an intermediate value. In effect, the conductivity of the reference memory cell is between that of an erased transistor and a written transistor.
In U.S. Pat. No. 5,081,610 the reference memory cell has an extra diode connected to what would have been a floating gate. This diode discharges the floating gate and has the same effect as programming it to an intermediate value, as mentioned in U.S. Pat. No. 4,434,479 above.
In U.S. Pat. No. 4,972,378 the reference memory cell is a single non-volatile transistor which has a physical structure differing from that of the data memory cells. This difference is such that the conductivity of the reference cell will be between that of the erased and written data memory cells.
In U.S. Pat. No. 5,172,338 a multi-state EEPROM uses reference cells whose threshold voltages and thus their conductivity are controlled by external circuitry. Multiple voltage thresholds are used to sense more than two binary states in a programmed data cell. In this implementation, a memory cell can store four distinct states.